The invention relates to the design and manufacture of integrated circuits.
An integrated circuit (IC) is a small electronic device typically formed from semiconductor material. Each IC contains a large number of electronic components that are wired together to create a self-contained circuit device. The objects on the IC are materialized as a set of geometric shapes that are placed and routed on the chip material. During placement and routing, the location and positioning of each geometric interconnect shape is identified and added to the design.
The IC design typically contains multiple layers of materials. Cut layers for an integrated circuit design are the metal plugs that connect two metal routing layers. Cut shapes must be connected to metal above and below the cut on the IC. This sandwich of two metal pieces and the cut (metal connecting the two shapes) is commonly called a “via.”
One goal of modern IC design is to minimize the occurrence of via failures in the manufactured IC product. Numerous types of via failures may occur during manufacturing. For example, a defect may be created during the manufacturing/fabrication process that physically causes an open circuit at the physical location of the via, e.g., the via may not be fully formed or sufficiently formed between the two layers of metal. This type of defect may cause the IC product to fail its intended operation or operate in a diminished capacity.
One conventional approach for addressing via failures is to utilize redundant vias in the IC design. The placement and routing steps for an IC design typically inserts a single cut via at each location requiring a connection between two metal layers of the design. Instead of using single cut vias, redundant vias can be used instead. This can be implemented in several different ways. One example approach is to add additional adjacent cuts at each single cut via location, thereby resulting in multiple single-cut vias that together form a multi-cut via, where the additional cuts provide redundancy in the event of a failure at the first cut. Another approach is to replace each single-cut via with a multi-cut via from a library of such multi-cut vias. In either approach, the resulting multi-cut via must comply with design rule requirements sufficient to pass a DRC check.
One problem with this approach is that not all single-cut via locations are eligible to be replaced with a multi-cut via or to receive additional adjacent via cuts. This situation may exist, for example, if the original single-cut via is very near other objects in the layout, and the addition of any additional cuts would cause a violation of a spacing rule. Therefore, it is quite possible that many single-cut vias will remain the IC design, increasing the risk of a via failure.
Therefore, there is a need for an improved method and mechanism to address and minimize via failures.
According to some embodiments of the invention, additional vias are inserted into the device in order to increase the number of cuts in an area to achieve a minimum or preferred percentage for each cut layer of the device's process. The additional vias can be inserted away from, but nearby, the original vias in the design. The present approach can be applied to minimize defects for both single-cut as well as multi-cut vias.
Other and additional objects, features, and advantages of the invention are described in the detailed description, figures, and claims.